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19-2234; Rev 1; 11/02
ECL/PECL Phase-Frequency Detectors
General Description
The MAX9382/MAX9383 are high-speed PECL/ECL phase-frequency detectors designed for use in highbandwidth phase-locked loop (PLL) applications. The devices compare a single-ended reference (R) and a VCO (V) input and produce pulse streams on differential up (U) and down (D) outputs. When integrated, the difference of the output pulse streams provides a control voltage proportional to input phase or frequency difference. Guaranteed minimum short pulse duration completely eliminates minimum phase difference requirements during the lock condition, maximizing loop jitter performance. The MAX9382/MAX9383 feature low propagation and reset delay, making them ideal for high-frequency clock synchronization use. The MAX9382 uses 100K logic levels, has a supply voltage range of VCC - VEE = 4.2V to 5.5V, and is pin compatible with Motorola's MCK12140. The MAX9383 uses 10H logic levels with a supply voltage range of VCC - VEE = 4.75V to 5.5V and is pin compatible with the MCH12140. The MAX9382/MAX9383 are available in industry-standard 8-pin SO and space-saving 8-pin MAX packages.
Features
o Guaranteed Minimum Pulse Width Eliminates Dead Band o 450MHz Typical Bandwidth with up to Phase Detection o 75k Internal Input Pulldown Resistors o 44mA Typical Supply Current o 2kV ESD Protection (Human Body Model) o Pin Compatible with MCK12140 and MCH12140 o Available in 8-Pin MAX and SO Packages
MAX9382/MAX9383
Ordering Information
PART MAX9382EUA* MAX9382ESA MAX9383EUA* MAX9383ESA TEMP RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 8 MAX 8 SO 8 MAX 8 SO
Applications
Precision Clock Distribution Central Office DSLAM DLC Base Station ATE
*Future product--contact factory for availability.
Functional Diagram
TOP VIEW
R R Q MAX9382 MAX9383 S U2 S Q R V D D D4 D 3 U U U1
Pin Configuration
MAX9382 MAX9383
8 7 6 5
VCC R V VEE
MAX/SO
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
ECL/PECL Phase-Frequency Detectors MAX9382/MAX9383
ABSOLUTE MAXIMUM RATINGS
VCC - VEE ............................................................................+6.0V Inputs (R, V).................................................(VCC) to (VEE - 0.3V) Continuous Output Current .................................................50mA Surge Output Current........................................................100mA Junction-to-Ambient Thermal Resistance in Still Air* 8-Pin MAX ..............................................................+221C/W 8-Pin SO ..................................................................+170C/W Junction-to-Ambient Thermal Resistance with* 500LFPM Airflow 8-Pin MAX ..............................................................+155C/W 8-Pin SO.....................................................................+99C/W Junction-to-Case Thermal Resistance 8-Pin MAX ...............................................................+39C/W 8-Pin SO....................................................................+40C/W Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C ESD Protection Human Body Model (R, V, U, U, D, D)............................2kV Soldering Temperature (10s) .......................................... +300C *Ratings are for single-layer board.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
MAX9382 DC ELECTRICAL CHARACTERISTICS
(VCC - VEE = 4.2V to 5.5V. Outputs loaded with 50 1% to VCC - 2V, unless otherwise noted. Typical values at VCC - VEE = 4.5V.) (Notes 1, 2, 3)
PARAMETER INPUTS (R, V) Input High Voltage Input Low Voltage Input High Current Input Low Current VIH VIL IIH IIL VIN = VIHMAX VIN = VILMIN 0.5 VCC 1.165 VCC 1.810 VCC 0.880 VCC 1.475 150 0.5 VCC 1.165 VCC 1.810 VCC 0.880 VCC 1. 475 150 0.5 VCC 1.165 VCC 1.810 VCC 0.880 VCC 1.475 150 V V A A SYMBOL CONDITIONS -40C MIN TYP MAX MIN +25C TYP MAX MIN +85C TYP MAX UNITS
OUTPUTS (U, U, D, D) Single-Ended Output High Voltage Single-Ended Output Low Voltage Differential Output Voltage POWER SUPPLY Supply Current IEE (Note 4) 43 56 44 56 45 58 mA VOH VIN = VIH or VIL VCC 1.085 VCC 0.990 VCC 0.880 VCC 1.035 VCC 0.960 VCC 0.880 VCC 1.035 VCC 0.940 VCC 0.880 V
VOL VOH VOL
VIN = VIH or VIL VIN = VIH or VIL
VCC 1.890 585
VCC 1.810 820
VCC 1.555
VCC 1.850 585
VCC 1.770 810
VCC 1.620
VCC 1.810 585
VCC 1.730 800
VCC 1.600
V
mV
2
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ECL/PECL Phase-Frequency Detectors
MAX9383 DC ELECTRICAL CHARACTERISTICS
(VCC - VEE = 4.75V to 5.5V. Outputs loaded with 50 1% to VCC - 2V, unless otherwise noted. Typical values at VCC - VEE = 5.2V.) (Notes 1, 2, 3)
PARAMETER INPUTS (R, V) Input High Voltage Input Low Voltage Input High Current Input Low Current VIH VIL IIH IIL VIN = VIHMAX VIN = VILMIN 0.5 VCC 1.230 VCC 1.950 VCC 0.890 VCC 1.500 150 0.5 VCC 1.130 VCC 1.950 VCC 0.810 VCC 1. 480 150 0.5 VCC 1.060 VCC 1.950 VCC 0.720 VCC 1.480 150 V V A A SYMBOL CONDITIONS -40C MIN TYP MAX MIN +25C TYP MAX MIN +85C TYP MAX UNITS
MAX9382/MAX9383
OUTPUTS (U, U, D, D) Single-Ended Output High Voltage Single-Ended Output Low Voltage Differential Output Voltage POWER SUPPLY Supply Current IEE (Note 4) 37 52 38 52 39 52 mA VOH VIN = VIH or VIL VIN = VIH or VIL VIN = VIH or VIL VCC 1.115 VCC 1.010 VCC 0.890 VCC 0.980 VCC 0.924 VCC 0.810 VCC 0.945 VCC 0.900 VCC 0.720 V
VOL VOH VOL
VCC 1.990 650
VCC 1.832 822
VCC 1.650
VCC 1.950 650
VCC 1.740 817
VCC 1.630
VCC 1.950 650
VCC 1.700 803
VCC 1.595
V
mV
MAX9382/MAX9383 AC ELECTRICAL CHARACTERISTICS
(Over specified DC input parameters, f = 100MHz, outputs loaded with 50 1% to VCC - 2V, unless otherwise noted.) (Note 5)
PARAMETER R Input to U Output Delay V Input to D Output Delay R Input to D Output Delay V Input to U Output Delay Minimum Pulse Duration SYMBOL CONDITIONS tPRU tPVD tPRD tPVU tPmin Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 -40C MIN 575 575 945 945 370 TYP 650 650 1120 1120 470 MAX 750 750 1320 1320 MIN 590 590 960 960 370 +25C TYP 660 660 1110 1110 450 MAX 780 780 1360 1360 MIN 635 635 1005 1005 370 +85C TYP 720 720 1150 1150 430 MAX 830 830 1360 1360 UNITS ps ps ps ps ps
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ECL/PECL Phase-Frequency Detectors MAX9382/MAX9383
MAX9382/MAX9383 AC ELECTRICAL CHARACTERISTICS (continued)
(Over specified DC input parameters, f = 100MHz, outputs loaded with 50 1% to VCC - 2V, unless otherwise noted.) (Note 5)
PARAMETER SYMBOL CONDITIONS usable phase difference range VIN = 200MHz, 50% duty cycle (Note 6) VIN = 400MHz, 50% duty cycle (Note 7) 20% to 80%, Figure 2 80 -40C MIN TYP MAX MIN +25C TYP MAX MIN +85C TYP MAX UNITS
Maximum Operating Frequency
fMAX
400
450
400
450
400
450
MHz
Phase Offset
30
70
28
60
28
60
ps
Added Random Jitter Output Rise/ Fall Time
tRJ
0.2
1.0
0.2
1.0
0.2
1.0
ps (RMS) ps
tR , t F
160
100
180
110
190
Note 1: Measurements are made with the device in thermal equilibrium. Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. Note 3: DC parameters are production tested at +85C. DC limits are guaranteed by design and characterization over the full operating temperature range. Note 4: All pins open except VCC and VEE. Note 5: Guaranteed by design and characterization. Limits are set to 6 sigma. Note 6: Phase offset is defined as the difference in propagation delay timing between the two input paths. It is measured between the U and D outputs at the differential crosspoint with a rising edge simultaneously applied at the R and V inputs. Note 7: Device jitter added to the input signal.
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ECL/PECL Phase-Frequency Detectors
Typical Operating Characteristics
(VCC - VEE = +4.5V (MAX9382) or VCC - VEE = +5.2V (MAX9383), VIH = VCC - 1.00V, VIL = VCC - 1.60V, fR = fV = 100MHz, outputs loaded with 50 to VCC - 2V, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE
MAX9382/83 toc01
MAX9382/MAX9383
MAX9382 TRANSITION TIME vs. TEMPERATURE
MAX9382/83 toc02
MAX9383 TRANSITION TIME vs. TEMPERATURE
MAX9382/83 toc03
45.0 42.5 SUPPLY CURRENT (mA) 40.0 37.5 35.0 32.5 30.0 -40 -15 10 35 60 MAX9383 MAX9382
150
200
TRANSITION TIME (ps)
TRANSITION TIME (ps)
125
RISE TIME
175
RISE TIME 150
100
FALL TIME
75
125 FALL TIME
50 85 -40 -15 10 35 60 85 TEMPERATURE (C) TEMPERATURE (C)
100 -40 -15 10 35 60 80 TEMPERATURE (C)
OUTPUT SHORT-PULSE DURATION vs. TEMPERATURE
MAX9382/83 toc04
PROPAGATION DELAY vs. TEMPERATURE
tPRU OR tPVD 725 PROPAGATION DELAY (ps) 700 675 650 MAX9382 625 600 MAX9383
MAX9382/83 toc05
550 OUTPUT SHORT-PULSE DURATION (ps) 525 500 MAX9382 475 450 425 400 -40 -15 10 35 60 MAX9383
750
80
-40
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
DIFFERENTIAL OUTPUT VOLTAGE vs. FREQUENCY
DIFFERENTIAL OUTPUT VOLTAGE (V)
MAX9382/83 toc06
OUTPUT PHASE ERROR vs. INPUT PHASE DIFFERENCE
MAX9382/83 toc07
830 820 810 MAX9382 800 790 780 770 0 500 1000 FREQUENCY (MHz) 1500
50
OUTPUT PHASE ERROR (ps)
MAX9383
40
30
20
10
0 2000 -4 -2 0 2 4 INPUT PHASE DIFFERENCE (ns)
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ECL/PECL Phase-Frequency Detectors MAX9382/MAX9383
Pin Description
PIN 1 2 3 4 5 6 7 8 NAME U U D D VEE V R VCC FUNCTION Inverting Up Output. Pulse stream is generated at this pin when fR > fV or V lags R in phase. Terminate with 50 resistor to VCC - 2V or equivalent. Noninverting Up Output. Pulse stream is generated at this pin when fR > fV or V lags R in phase. Terminate with 50 resistor to VCC - 2V or equivalent. Inverting Down Output. Pulse stream is generated at this pin when fV > fR or R lags V in phase. Terminate with 50 resistor to VCC - 2V or equivalent. Noninverting Down Output. Pulse stream is generated at this pin when fV > fR or R lags V in phase. Terminate with 50 resistor to VCC - 2V or equivalent. Negative Supply Single-Ended VCO Input Single-Ended Reference Input Positive Supply. Bypass from VCC to VEE with 0.1F and 0.01F ceramic capacitors. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device.
Detailed Description
The MAX9382/MAX9383 are high-speed phase or frequency detectors. The MAX9382 is compatible with 100K logic and has a power-supply range of VCC - VEE = 4.2V to 5.5V. The MAX9383 is compatible with 10H logic with a power-supply range of VCC - VEE = 4.75V to 5.5V. Both devices are specified to function from -40C to +85C. Each device is symmetrical; the R and V input functions may be swapped, together with the U and D output functions, and the inputs and outputs relabeled. Because of this device symmetry, a necessary condition for correct phase measurement operation is that the U and D outputs must both be high (state 0 condition) when the rising edge of the leading input is received. This condition is automatically generated when the two inputs are at different frequencies.
detect phase differences up to 2. The application frequency and the characteristics of the device internal reset circuits determine the usable input phase difference range.
Frequency Detection
Figure 4 is the state diagram for the MAX9382/ MAX9383. With the two inputs at the same frequency, and input R leading input V, the device toggles between states 0 and 2. Similarly, if input R lags input V, the device toggles between states 0 and 1. With the two inputs at different frequencies, the output becomes a function of the frequency difference. The normalized ideal transfer function is given by: VOUT _ AVE = 1and VOUT _ AVE = 1fV for fR > fV 2fR fR for fV > fR 2fV
Phase Detection
The MAX9382/MAX9383 are intended for use in highbandwidth PLL applications. These devices compare a single-ended VCO input (V) to a single-ended reference input (R) to determine the phase or frequency relationship between V and R. The device differential outputs U, U and D, D provide pulse trains with duty cycle proportional to the phase or frequency difference between R and V. These outputs are the up and down signals required to control the system VCO. Figure 1 shows typical waveforms when V leads R and V lags R. Subtracting and integrating these two outputs provide the necessary VCO control signal. Figure 3 shows the device transfer function obtained. The detector can
6
Output Pulses
When inputs R and V are at the same phase and frequency, outputs U, U and D, D produce a stream of minimum duration pulses that occur at the rising edges of the input waveforms. This is the lock condition. If either input starts to lead the other in phase, the width of pulses on the corresponding output (U for R input, D for V input) increases in proportion to the phase difference. In a PLL implementation, these outputs direct the
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ECL/PECL Phase-Frequency Detectors MAX9382/MAX9383
R V U U D D tPRU a) INPUT AND OUTPUT WAVEFORMS FOR V LEADING R tPVU tPmin
R V U U D D tPVD b) INPUT AND OUTPUT WAVEFORMS FOR V LAGGING R tPRD tPmin
Figure 1. Typical Waveforms when fR = fV
system VCO to increase or decrease frequency to maintain the lock condition. The minimum output pulse duration is an important parameter for the design of the signal processing functions, which follow the phase detector. When controlling a charge-pump integrator, a detector can produce a dead-zone characteristic at the lock condition if the minimum pulse width is too short. MAX9382/MAX9383 eliminate this dead-zone characteristic, and the resulting phase offset at lock, by providing a well-defined minimum output pulse width.
U-U OR D-D 80% 20% tR tF 80% 20%
Figure 2. Output Transition Times
PECL systems, connect VCC to a positive supply and VEE to ground.
Applications Information
The MAX9382/MAX9383 input and output levels are defined to be relative to the positive supply voltage. In ECL systems, the positive supply voltage is conventionally chosen to be system ground. This arrangement produces the best noise immunity, since ground is normally a system-wide reference voltage. Operate the devices with VCC connected to ground and VEE connected to a negative supply for ECL systems. With
Power-Supply Bypassing
Adequate power-supply bypassing is necessary to maximize the performance and noise immunity of ECL devices. This is particularly true of a PECL system where the power-supply voltage is used as a reference. Bypass VCC to VEE with high-frequency surface-mount ceramic 0.1F and 0.01F capacitors in parallel and as close to the device as possible, with the 0.01F capaci-
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7
ECL/PECL Phase-Frequency Detectors MAX9382/MAX9383
Circuit Board Traces
fV > fR OR V LEADS R AVG (U) fV < f R OR V LAGS R VOH VOL VOH VOL VOH - VOL AVG (U - D) 0 VOL - VOH 4
AVG (D)
Input and output trace characteristics affect the performance of ECL/PECL devices. Connect each of the detector's inputs and outputs to a 50 characteristic impedance trace. Avoid impedance discontinuities, maintain the distance between differential traces, avoid sharp corners, and keep the electrical length of the differential traces matched. This maximizes commonmode noise rejection and reduces signal skew. Trace vias cause impedance discontinuities, so keep the number of vias in the 50 traces to a minimum. Reduce reflections by maintaining the 50 characteristic impedance through connectors and across cables.
Output Termination
Terminate outputs through 50 to VCC - 2V or use an equivalent Thevenin termination. When a single-ended signal is taken from a differential output, terminate both outputs. For example, if the U output of the MAX9382 or MAX9383 is connected to a single-ended input, terminate both the U and U outputs.
-4
-3
-2
-
0
2
3
Figure 3. Average Output Voltage vs. Phase Difference
tor closest to the device pins. Use multiple parallel vias for ground plane connection to minimize inductance.
Chip Information
TRANSISTOR COUNT: 706 PROCESS: Bipolar
R STATE 2 U=0 D=1 VCO UP STATE 0 U=1 D=1
V STATE 1 VCO DOWN U=1 D=0
R
V
V
R
Figure 4. MAX9382/MAX9383 State Diagram
8
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ECL/PECL Phase-Frequency Detectors
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
8LUMAXD.EPS
MAX9382/MAX9383
8
4X S
8
INCHES DIM A A1 A2 b c D e E H MIN 0.002 0.030 MAX 0.043 0.006 0.037
MILLIMETERS MAX MIN 0.05 0.75 1.10 0.15 0.95
y 0.500.1 0.60.1
E
H
1
0.60.1
1
D
L
S
BOTTOM VIEW
0.014 0.010 0.007 0.005 0.120 0.116 0.0256 BSC 0.120 0.116 0.198 0.188 0.026 0.016 6 0 0.0207 BSC
0.25 0.36 0.13 0.18 2.95 3.05 0.65 BSC 2.95 3.05 4.78 5.03 0.41 0.66 0 6 0.5250 BSC
TOP VIEW
A2
A1
A
e
c b L
SIDE VIEW
FRONT VIEW
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, 8L uMAX/uSOP
APPROVAL DOCUMENT CONTROL NO. REV.
21-0036
J
1 1
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9
ECL/PECL Phase-Frequency Detectors MAX9382/MAX9383
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
SOICN .EPS
INCHES DIM A A1 B C e E H L MAX MIN 0.069 0.053 0.010 0.004 0.014 0.019 0.007 0.010 0.050 BSC 0.150 0.157 0.228 0.244 0.016 0.050
MILLIMETERS MAX MIN 1.35 1.75 0.10 0.25 0.35 0.49 0.19 0.25 1.27 BSC 3.80 4.00 5.80 6.20 0.40 1.27
N
E
H
VARIATIONS:
1
INCHES
MILLIMETERS MIN 4.80 8.55 9.80 MAX 5.00 8.75 10.00 N MS012 8 AA 14 AB 16 AC
TOP VIEW
DIM D D D
MIN 0.189 0.337 0.386
MAX 0.197 0.344 0.394
D A e B A1 L C
0-8
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, .150" SOIC
APPROVAL DOCUMENT CONTROL NO. REV.
21-0041
B
1 1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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